Lateral double-diffused metal oxide semiconductor (LDMOS) transistors require that the LDMOS transistors have a low on resistance, a high off resistance, and a large electrical safe operating area. To increase the current handling capability of the LDMOS transistors on an integrated circuit, a number of LDMOS transistors are often tied together forming, for example, multi-fingered LDMOS. With the LDMOS transistors connected in parallel, the current flow can be shared among the various LDMOS transistors. To ensure the proper distribution of current among the various LDMOS transistors, it is important that the threshold voltage (Vt) of the individual LDMOS transistor structures be closely matched.
The threshold voltage (Vt) of the LDMOS transistor is set by the multiple ion implantation processes used to form the transistor channel region. During the multiple ion implantation processes, a patterned photoresist (PR) masking layer is formed over the substrate and the dopant species are implanted through patterned openings formed in the PR masking layer. In forming the LDMOS transistors required for high current applications, a major limitation to obtaining closely matched threshold voltages is the variation in the photoresist sidewall angle of the various openings through which the dopants are implanted. For example, the photoresist sidewall angle is significantly decreased depending on local resist density, such as after the photoresist hard bake step of a conventional photolithography process.
Thus, there is a need to overcome these and other problems of the prior art and to provide methods for forming LDMOS transistors with closely matched threshold voltages.